Topic SMM from CPU FAQ base
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— RU.HACKER (2:5020/299) —————————————————————————————————————————— RU.HACKER — From : Roman Ibragimov 2:5050/9.9 Wed 10 Apr 96 22:31 Subj : about SMM ———————————————————————————————————————————————————————————————————————————————— Çäîðîâî, Alexey! Òû, êàæåòñÿ, ñàáæ ïðîñèë? Âîò îòñêàíèðîâàë ñòàòåéêó èç Intel Solutions European Edition çà ìàé-èþíü '93ã. === Cut === A Look at Intel's System Managment Mode SMM in today's mobile computers allows the machines to shut down instantaneously to a level at which only milliwatts (thousandths of a watt) of electricity are consumed. In this "sleep" mode, today's mobile computers can suspend activities for weeks while on a single battery charge and then immediately spring to life at the touch of a button. This instantaneous on and off capability is being designed into desktop computers as well to cut their electrical power consumption dramatically. SMM provides an environment for executing power management software that does not interfere with the perfor mance of the operating systems or application programs. It's versatile and can be used for other applications as well, such as debugging, I/O emulation, embedded operating system and virus detection. The following is an excerpt of Chapters 4 and 5 in Yuen's book. Innovation and Power Management SMM is a unique operating mode that lets the CPU execute code transparently from the operating system and application software; thus, power-management programs run smoothly. This function is an improvement over the software controlling the first-generation power-management hardware, which often conflicted with the operating system and application programs, leading to system crashes and data corruption. The root of the problem was in the implementation of the power-management hardware. The nonmaskable interrupt (NMI) was used to perform functions such as servicing a stand-by button, turning off power to a peripheral and slowing or stopping the CPU clock. Using NMI in this way saved power but caused compatibility problems: the software servicing the NMI was not isolated from the operating system and application software. Using NMI, manufacturers were forced to develop many versions of power-management drivers to accommodate different operating environments. With SMM, the software and the hardware do not even know they are in SMM. It does not require special software drivers and reduces the cost of developing power-management software. The powerful resources offered by SMM lend a great deal of flexibility in designing power-management systems. The power-management software can be written independently of BIOS and operating systems, and thus reduces development time. Software can dynamically control the CPU clock speed and the distribution of power to different parts of the system, such as memory and peripherals, based on a particular system profile. The Basics The basic components of the SMM architecture are system management interrupt (SMI) to invoke SMM, a unique address space for storage and execution of SMM routines, and a new instruction called RSM (opcode 0FAAh) to exit from SMM. SMM supports collaboration between system resources and the CPU. When the system hardware requires service from the SMM program, it sends a SMI to the CPU. The CPU then enters the SMM, executes a SMM routine to service the request and exits SMM. System hardware and software can explicitly generate SMIs to execute a powermanagement routine. Applications Various applications make use of the transparent property of SMM. For example, the SMM has proved useful for debugging system designs. A debugger running in SMM offers several benefits over traditional software debuggers and incircuit emulators (ICEs). Another example of an application improved by the SMM is a fail-safe backup mechanism. Losing data during a power outage can be a nightmare for a computer user who does not have an uninterruptible power supply. Using a small backup battery can keep the system active long enough for the CPU to save all volatile data to a permanent storage device before powering down the system. After power is resumed to the system, the data and machine state can be restored to where they were prior to the power failure. Using the SMM software, a monitor circuit can be designed that generates a SMI whenever a power failure is detected. The SMI can then be used to activate the backup battery and invoke the fail-safe backup program, which runs in SMM. Entering SMM Enter SMM by activating the SMI# signal, a falling-edge-triggered signal recognized only on instruction execution boundaries. A SMI can be signaled directly by asserting the SMI# pin. While in SMM, the CPU ignores all SMIs until the new instruction, called RSM (opcode 0FAAh), is exe cuted. After a SMI is recognized, the CPU enables System Management RAM (SMRAM) address space, saves the CPU state in the processor state area (PSA), enables SMM and starts executing instructions at system address 38000H. (The SMI# pin remains activated until the software running in SMM exits SMM.) Upon entering SMM, the CPU automatically saves registers DR6 and DR7 in SMRAM (these registers should not be modified). Debug registers DR[0:5] are not saved automatically; they should be saved by power-management (or SMM) software before the system goes into suspend. After entering SMM, the PE bit in the CR0 register is automatically cleared and CS:IP is initialized to 3000H:8000H, causing instruction execution to start at physical address 38000H. All SMM software must be written so that the first instruction is located at 3000H:8000H when SMM is enabled. To protect against the problem of system hang-ups, the CPU blocks external interrupts generated via the INTR signal after entering SMM. Software routines running in SMM cannot depend on interrupt-driven features. For example, a timing loop that depends on an interrupt from the real-time clock will not work inside SMM. If the set interrupt flag (STI) instruction is executed while the system is in SMM, the protection against external interrupts is overridden, and the CPU will respond to them. To avoid hanging up the system, don't use the STI instruction while in SMM. After the CPU enters SMM and saves its state in the PSA, it sets several registers to predefined values. These values are sufficient to allow program execution, but additional initialization may be needed (see the "Predefined Register Values" table). Also, the PE bit in the CR0 register and the DR7 register is cleared. System Management RAM Address Space The SMRAM address space is a separate memory address space provided on the CPU that is used for storage and execution of SMM software routines. It is distinct from the physical memory address space to ensure that software running in SMM does not conflict with the operating system or application software. The SMRAM can be located in either on-board or offboard memory; the size of the SMRAM can be 32 or 64 Kbytes if off-board memory is used, and 64 Kbytes if onboard memory is used. After SMM is enabled, the SMRAM address space is mapped to the physical address space from 30000H to 3FFFFH (64 Kbytes), or from 38000H to 3FFFFH (32 Kbytes). Unlike real-address mode, the CPU can access or jump anywhere within the 4-Gbyte logical address space in SMM. The CPU can indirectly access or perform a nearjump anywhere within the 4-Gbyte logical address space. In SMM, the address generation is the same as in real-address mode, without the 64-Kbyte limit. The value loaded into the selector register is shifted 4 bits and is added to the effective address. The effective address can also be generated indirectly using a 32-bit register. The selector is limited to 16 bits. If a call is made, only 16 bits are pushed for a return. Exiting SMM The only way to exit SMM is to execute the resume instruction (RSM), which restores the CPU registers to their original states. The RSM instruction has two options associated with it that are enabled or disabled by the programmer writing to the PSA. The first option enables the SMM program to return to the halt state through the use of the halt auto-restart slot if the SMI occurred when the CPU was in the halt state. The second option enables the I/O instruction that caused the SMI to be re-executed. Upon entering SMM, the CPU automatically initializes the I/O trap restart slot to 0H. Your system software should set the I/O trap restart slot to 0FFH only if the SMI was caused by an I/O trap. Upon exiting SMM, program execution always returns to the program that was interrupted by the SMI. However, program execution can be passed to a different program. For a program running in real mode, the CPU can be directed to a different program by modifying the instruction pointer in the PSA to point to the beginning of another program. After exiting SMM, the CPU will then jump to the new program instead of returning to the interrupted program. To avoid a system crash, exit SMM without going back to the interrupted program by having the SMM program generate a CPU reset prior to re-enabling the CPU. The CPU reset then forces the CPU to exit SMM without returning to the original application. Conclusion The instantaneous on and off capability provided with SMM offers an energy-efficient solution to desktop computers' high power consumption. SMM gives programmers who use these "green machines" the ability to execute power-management software without the implementation problems they previously experienced. Ú——————————————————————————————————————————————¿ ³ Predefined Register Values in SMM for SL CPU ³ Ã———————————————Â————————————————Â—————————————´ ³ Selector ³ Base ³ Limit, Gb ³ Ã———————————————Å————————————————Å—————————————´ ³ CS ³ 30000H ³ 4 ³ ³ DS ³ 0H ³ 4 ³ ³ ES ³ 0H ³ 4 ³ ³ FS ³ 0H ³ 4 ³ ³ GS ³ 0H ³ 4 ³ ³ SS ³ 0H ³ 4 ³ À———————————————Á————————————————Á—————————————Ù === Cut === Áóäü çäîðîâ. Roman. --- Çîëîòîé ðåäàêòîð, âåðñèÿ 2.50+ * Origin: Hå ïðèñòàëî íàì ïèñàòü íåïðèñòîéíîñòè (2:5050/9.9)
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