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Topic P5_H from CPU FAQ base

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— SU.HARDW (2:5020/78.7)  ——————————————————————————————————————————— SU.HARDW —
 From : Leonid A. Broukhis                  2:5020/6.14     Sat 29 May 93 18:56 
 Subj : Pentium Processor - what's new?                                         
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From: leo@ipmce.su (Leonid A. Broukhis)

  [Quoted from USENET newsgroup comp.arch]

Appendix H

This appendix describes the privileged-mode architectural extensions
which have been introduced with the Pentium(tm) architecture,
which are not present in the Intel386(tm) or Intel486(tm)
architectures.  These consist of a new register set, the Microcode
Patch Registers (MPR's), and two new instructions:

PMPR    Push Patch Register
EMX     Execute Microcode Extension

In the design of the Pentium(tm) processor, historical averages were
used to predict the number of fatal microcode bugs which could be
expected in the production silicon.  At the equivalent of 360K bytes
of microcode data, it was anticipated that there would be
approximately 25 fatal bugs.  32 patch registers were included to
allow for the remapping of up to 32 microinstruction words.

Prior to enabling interrupts and protected-mode addressing, it is
expected that power-on initialization software will load the MPR's
with data appropriate for that chip's revision level and stepping.
Use of the MPR registers for performance enhancement is reserved
for Intel.  There is no support for customer-generated patches to the
microcode.

H.1  Microcode Patch Registers

The Microcode Patch Registers (MPR) consist of a 256-bit instruction
field and a 12-bit address field, as shown in Figure H-1.

[Figure H-1 deleted.]

Prior to enabling interrupts or protected-mode addressing, the
power-on initialization software loads the MPR registers with
data appropriate for the chip's revision level and mask stepping
(see Chapter 13, "Reset Initialization" for more information).

The 256-bit data field of the MPR register specifies the micro-
instruction bit pattern which is to replace the pattern stored
in the chip's Microcode ROM (MR).  The 12-bit address field
specifies the Microcode ROM Address (MRA) of the microinstruction
word to be replaced.

H.2  Microcode Patch Instructions

The Pentium(tm) architecture contains two new privileged
instructions for handling the microcode patching mechanism:

*    PMPR -- Push Microcode Patch Register
*    EMX  -- Execute Microcode Extension

Upon power-on initialization, the Microcode Patch Register Pointer
(MPRP) is cleared, so it is pointing to MPR register 0.  Every time
the PMPR instruction is executed, the 256-byte microcode image at the
effective address referenced by the mod R/M byte is loaded into
the MPR register addressed by the MPRP register, then the MPRP
register is incremented.

H.2.1  PMPR Instruction

[bit box and pseudo-code deleted]

The PMPR instruction loads the MPR register pointed to by the
MPRP register with the 256-byte image referenced by the mod R/M
byte.  No flags are affected.

H.2.2  EMX Instruction

[bit box and pseudo-code deleted]

The EMX instruction executes the microcode sequence stored at
address 0F80H in the microcode ROM.  This instruction is reserved
by Intel and must not be executed.

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