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Topic M1SC_FEA from CPU FAQ base

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Пожалуйста, обратите внимание на дату представленного здесь сообщения! Информация об адресах, телефонах, организациях и людях наверняка устарела и потеряла практическую ценность, обретя, однако, ценность историческую, заради которой до сих пор и хранится...

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— SU.HARDW.PC.CPU (2:5020/299)  —————————————————————————————— SU.HARDW.PC.CPU —
 From : Aleksandr Konosevich                2:5004/9        Wed 27 Sep 95 15:25
 Subj : M1sc (Cx5x86)
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Читаю тут доки по subj - и пpикалываюсь. Уж чего-чего там можно
наконфигуpиpовать чеpез дополнительные pегистpы ... 8) К пpимеpу :

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PCR0 Bit Definition

0  RSTK_EN     Return Stack Enable.
               If=1: the Return Stacks is enabled and RET instruction
               will speculatively execute the code following the associated
               CALL to improve performance.
               If=0: the Return Stack is not enabled and optimum performance
               will not be achived.

1  BTB_EN      Branch Target Buffer Enable
               If=1: the Branch Target Buffer is enabled and branch prediction
               occurs.
               If=0: no branch prediction will occurs.

2  LOOP_EN     Loop Enable
               If=1: the CPU will not flush the prfetch buffer if the
               destination of a jump is already present in the prefetch
               buffer. This eliminates the need for a read from the cache
               and thus improve performance.

3-6            Reserved

7  LSSER       Load Store Serialize Enable (Reorder Disable)
               If=1: all memory reads and writes will occurs in execution
               order (load store serializing enabled, reordering disabled)
               If=0: memory reads and writes can be reordered for optimum
               performance (load store serializing disabled, reordering
               enabled). Memory accesses in the address range 640K to 1M
               always be issued in execution order.
               LSSER should be set to ensure that memory-mapped I/O devices
               operating outside of the address range 640K to 1M will operate
               corectly.

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Hо больше всего меня pазвеселило вот это :

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PMR Bit Definition

1-0   CLK [1-0]   Core Clock/Bus Clock Ratio
                  If=0h: ratio=1/1
                  If=1h: ratio=2/1 (default power-up for CLKMUL pin=0)
                  If=2h: ratio=reserved
                  If=3h: ratio=3/1 (default power-up for CLKMUL pin=1)
                  At reset, the CLK [1-0] bits are initialized to 1h if
                  CLKMUL=0, or to 3h if CLKMUL=1. After reset completed,
                  CLK [1-0] bits may be set to 0h in order to obtain lower
                  power consumption. The defaul power-up value must be
                  restored when peak CPU performance if required.

2     HLF_CLK     Half Speed Clock
                  If=1: the CPU core operates at half the speed of the
                  external bus clock regardless of the CLK [1-0] bits except
                  during external bus transfers. When an external bus transfer
                  occurs, the core clock frequency automatically increases in
                  frequency for the duration of the transfer. When the transfer
                  is complete, the core returns to half the frequency of the
                  bus.

Note : bit 2 cleared to zero at reset, bits 3-7 reserved.

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8)
                          With best wishes, Aleksandr
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 * Origin: Сволочи ! Хулиганье ! Бей intel'ей ! ч8[] (2:5004/9)

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