Topic CX5X86R from CPU FAQ base


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SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Aleksandr Konosevich 2:5004/9 Wed 31 Jan 96 17:43 Subj : ppp p pp Cx5x86, 1 pp pp p subj. p p - p p p , .. /p. , Copyright (C) Cyrix Corporation, portional copyright (C) Aleksandr K. Konosevich, p pp (C) - , p p/ .. . 8) p p p p Cyrix p pp. ----------------------------------------------------------------------------- , ppp p Cyrix p pp, p pp pp x86-. , pp (.. pp p p ) - pp p / (IN/OUT ..) p ppp p p pp /. , p, p ppp ( pp - ppp/ppp i188/i186/Am188/Am186 ..) ppp pp p pp Cx5x86 , p pp SLC/DLC/DX/DX2 - p p 22h 23h /. p p 22h p pp, p 23h p / p pp. Cx5x86 p pp, __ 1 MAPEN0 CCR3 ( pp *). H p p pp Cx5x86 p pp . , X, ppp p Cyrix p pp Cyrix. ; ; Reg & Bit in register ; Index ; 7 6 5 4 3 2 1 0 ; ; PCR0 ; 20h* LSSER X X X X LOOP_EN BTB_EN RSTK_EN ; ; CCR1 ; C1h X X X X MMAC SMAC USE_SMI X ; ; CCR2 ; C2h USE_SUSP BWRT X WT1 SUSP_HALT LOCK_NW USE_WBAK X ; ; CCR3 ; C3h MAPEN3 MAPEN2 MAPEN1 MAPEN0 SMM_MODE LINBRST NMI_EN SMI_LOCK ; ; CCR4 ; E8h* X X X DTE_EN MEM_BYP IORT2 IORT1 IORT0 ; ; SMAR0 ; CDh A31 A30 A29 A28 A27 A26 A25 A24 ; ; SMAR1 ; CEh A23 A22 A21 A20 A19 A18 A17 A16 ; ; SMAR2 ; CFh A15 A14 A13 A12 SIZE3 SIZE2 SIZE1 SIZE0 ; ; PMR ; F0h* X X X X X HLF_CLK CLK1 CLK0 ; ; DIR0 D e v i c e i d e n t i f i e r ; FEh ; ; DIR1 D e v i c e r e v i s i o n ; FFh ; pp /, p (pp DIR0, DIR1) - . H pp pp, pp DIR1/DIR0 p DOS' : .model tiny .code org 100h .286 ; ; Copyright (C) 1995 Aleksandr K. Konosevich ... ;) ; start: cld cli mov dx, 0022h ; I/O base mov al, 0FEh ; Index of DIR0 register out dx, al ; Send index of DIR0 to CPU inc dx ; DX -> 23h, AF -> 0 in al, dx ; Read contents of DIR0 mov di, offset DIR0 ; Place for printable DIR0 value call hex ; Convert to printable data mov al, 0FFh ; Index of DIR1 register dec dx ; DX -> 22h out dx, al ; Send index inc dx ; DX -> 23, AF -> 0 in al, dx ; Read DIR1 mov di, offset DIR1 ; Place for DIR1 value call hex ; Convert to printable sti mov dx, offset mess ; Output message to screen via DOS mov ah, 09h int 21h retn ; Exit to DOS hex label near ; Subroutine for conversion of AL ; to printable HEX ASCII aam 10h xchg al, ah call hex_low mov al, ah hex_low: aaa aas adc al, '0' daa stosb retn mess db 0Ah, 0Dh, 'Value of DIR0 register is ' DIR0 db 'XXh.' db 0Ah, 0Dh, 'Value of DIR1 register is ' DIR1 db 'YYh.$' end start DIR0 : 29h or 2Bh, pp p , 2Dh or 2Fh - p p. IMHO, p p Cx5x86 PGA ( ), p - PQFP-. p - IMHO, .. Cx5x86 PQFP pp . pp, .. - p. :) With best wishes, Aleksandr P.S. , p pp pp, p . |) --- * Origin: ' ! ! !' (2:5004/9) SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Aleksandr Konosevich 2:5004/9 Fri 02 Feb 96 18:22 Subj : ppp p pp Cx5x86, 2 , p ... :) pp p , p : Performance Control Register 0 (PCR0), Index = 20h ------------------- PCR0 Bit Definition 0 RSTK_EN Return Stack Enable. If=1: the Return Stacks is enabled and RET instruction will speculatively execute the code following the associated CALL to improve performance. If=0: the Return Stack is not enabled and optimum performance will not be achived. 1 BTB_EN Branch Target Buffer Enable If=1: the Branch Target Buffer is enabled and branch prediction occurs. If=0: no branch prediction will occurs. 2 LOOP_EN Loop Enable If=1: the CPU will not flush the prfetch buffer if the destination of a jump is already present in the prefetch buffer. This eliminates the need for a read from the cache and thus improve performance. 3-6 Reserved 7 LSSER Load Store Serialize Enable (Reorder Disable) If=1: all memory reads and writes will occurs in execution order (load store serializing enabled, reordering disabled) If=0: memory reads and writes can be reordered for optimum performance (load store serializing disabled, reordering enabled). Memory accesses in the address range 640K to 1M always be issued in execution order. LSSER should be set to ensure that memory-mapped I/O devices operating outside of the address range 640K to 1M will operate corectly. ----------------------------- p ... With best wishes, Aleksandr --- * Origin: ' ! ! !' (2:5004/9) SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Aleksandr Konosevich 2:5004/9 Mon 05 Feb 96 17:37 Subj : ppp p pp Cx5x86, 3 , p ... :) pp p , p : Configuration Control Register 1, Index = C1h ------------------- CCR1 Bit Definition 1* USE_SMI Enable SMM Pins If=1 : SMI# input/output pin and SMADS# output pin are enabled. If=0 : SMI# input pin ignored and SMADS# output pin floats. 2* SMAC System Management Memory Access If=1 : Any access to addresses within the SMM memory space cause external bus cycles to be issues with SMADS# output active. SMI# input is ignored. If=0 : No effect on access. 3* MMAC Main Memory Access If=1 : All data accesses which occur within an SMI service routine (or when SMAC=1) access main memory instead of SMM memory space. If=0 : No effect an access. Note : Bits 0, 4-7 are reserved. Bit 1-3 are cleared to 0 at reset. * Note : Access enabled by CCR3, bit 0, SMI-Lock bit. ----------------------------- p ... With best wishes, Aleksandr --- * Origin: ' ! ! !' (2:5004/9) SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Sergey Kutikin 2:5020/324.16 Wed 07 Feb 96 01:28 Subj : CpuId p ! Tue 06 Feb 1996 Aleksandr Konosevich wrote in a message to Sergey Kutikin: AK> ... p CPUID ( p Cx5x86/Cx6x86) AK> Cx6x86, p p subj AK> "p " ( - CCR4, Inv OpCode AK> p). Cx5x86 (DIR1 = 13h) p subj AK> . " CCR 4 Bit 7 - CPUIDEN CPUIDEN - If set,this bit enables writing to bit 21 of the EFLAG register(indicating that the cpu supports the CPUID instruction) and the CPUID instruction will execute normally. If clear,bit 21 of the EFLAG register is not writable and the CPUID instruction is an invalid opcode. * This bit is only available on Stepping 1 and later versions of the 5x86 CPU.The CPUID instruction is disabled on all prior devices." - p , p :) p . , Cx6x86-100 (m/b P55SP4 ASUS rev.1.4,BIOS rev.3.06) ,pp : Norton SI v.8.0 - 676 Power Meter 1.81 - 66.3 MIPS Best regards,Sergey --- GEcho 1.11+ * Origin: Net v zhizni schastya... (2:5020/324.16) SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Sergey Kutikin 2:5020/324.16 Fri 02 Feb 96 02:08 Subj : CpuId p ! Thu 01 Feb 1996 Alex Gerasimov wrote in a message to Alexander Amelkin: AG> M1sc p. "3.1.2 Identifying a Cyrix CPU After determining that a Cyrix CPU exists,its DIRs can be read to identify its type.The DIRs are a subset of the 5x86 configurations registers.The 5x86 DIRs exist at register indexes FEh and FFh..... and contain device identification,stepping and revision information... 3.2 CPU Identification Using CPUID Instruction The CPUID instruction will not be available until Stepping 1 of the device.Stepping 1 is indicated by DIR1=0001xxxx. .... ....The EBX,ECX,and EDX registers contain the vendor identification string "CyrixInstead". .... " ("5x86 CPU BIOS Writer's Guide" (c) Cyrix Corp.) Best regards,Sergey --- GEcho 1.11+ * Origin: Net v zhizni schastya... (2:5020/324.16) SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Aleksandr Konosevich 2:5004/9 Sat 10 Feb 96 16:46 Subj : ppp p pp Cx5x86, 4 , p ... :) pp p , p : Configuration Control Register 2, Index = C2h ------------------- CCR2 Bit Definition 1 USE_WBAK Enable Write-Back Cache Interface Pins If=1 : Enable INVAL and WM_RST input pins, CACHE# and HITM# output pins. When enabling write-back cache mode, the USE_WBAK bit must be set prior to setting the NW bit in CR0. If=0 : INVAL and WM_RST input pins are ignored, and CACHE# and HITM# output pins float. 2 LOCK_NW LOCK NW Bit If=1 : Prohibits changing the state of the NW bit in CR0. 3 SUSP_HALT Suspend on HALT If=1 : CPU enters suspend mode following execution of HALT instruction. 4 WT1 Write-Trough Region 1 If=1 : Forces all writes to the address region between 640 KBytes to 1 MByte that hit in the on-chip cache to be issued on the external bus. 6 BWRT Enable Burst Write Cycles If=1 : Enables use of 16-byte burst write-back cycles. 7 USE_SUSP Enable Suspend Pins If=1 : SUSP# input and SUSPA# output are enabled. If=0 : SUSP# input is ignored and SUSPA# output floats. Note : Bits 0 and 5-7 are reserved. Bit 1-4, 6 and 7 are cleared to 0 at reset. ----------------------------- p ... With best wishes, Aleksandr --- * Origin: ' ! ! !' (2:5004/9) SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Lesha Bogdanow 2:5095/9 Wed 14 Feb 96 01:59 Subj : Cyrix 5x86 (M1SC) p All! , p, subj, , Alexandr Konosevich , (p, p): === Cut === The Cyrix 5x86 processor contains the following registers: ------------------------------------------------------------------------------ name reg# description ------------------------------------------------------------------------------ CCR1 C1h configuration control register #1 (=0h after reset) bit7..4 reserved bit3 MMAC - enable main memory accesses when CCR1.SMAC=1 1=enabled, 0=disabled bit2 SMAC - enable SMM memory accesses with SMAADS# active 1=enabled (SMI# ignored), 0=disabled bit1 SMI - enable SMM pins (SMI# I/O pin and SMADS# output pin) 1=enabled, 0=disabled (=pins float) bit0 reserved ------------------------------------------------------------------------------ CCR2 C2h configuration control register #2 (=0h after reset) bit7 SUSP - enable SUSP# input pin and SUSPA# ouput pin 1=enabled, 0=disabled (=pins float) bit6 BWRT - enable (16byte WB) burst write cycle 1=enabled, 0=disabled bit5 reserved bit4 WT1 - caching for 640K..1M area 1=force all writes to 640K..1M area that hit in cache issued on the external bus 0=disabled bit3 HALT - enable entering suspend mode on HLT inctructions 1=enabled, 0=disabled bit2 LockNW - prohibits changing the state of the CR0.NW bit 1=enabled (=prohibited), 0=disabled (=allowed) bit1 WBAK - enable WB cache pins (INVAL, WM_RST, HITM#) 1=enabled, 0=disabled (=pins float) bit0 reserved ------------------------------------------------------------------------------ CCR3 C3h configuration control register #3 (=?0h after reset) bit7..4 MAPEN - select active control register set for D0h..FDh 0001=default (others are not valid at the moment) bit3 SMIACT - enable Intel compatible SMM (i486SL?) 1=enabled, 0=disabled bit2 LINBRST - enable linear address sequence for burst cycles 1=enabled, 0=disabled bit1 NMIEN - enable NMI during SMM 1=enabled, 0=disabled bit0 SMI_LOCK - SMM register lock 1=CCR1.bit3..1 and CCR3.bit1 can't be changed in SMM; CCR3.bit0 can be changed in SMM; only RESET clears it! 0=disabled CCR4 E8h configuration control register #4 bit7..6 reserved bit5 FP_FAST - enable fast FPU exception reporting 1=enabled, 0=disabled bit4 DTE_EN - enable directory table entry cache 1=enabled, 0=disabled bit3 MEM_BYP - enable memory bypassing 1=enabled, 0=disabled bit2..0 IORT - I/O recovery time xxx=0..7 bus clock cycles ------------------------------------------------------------------------------ CR F0h configuration register bit7 SMCC - self modifying code checking 1=disabled, 0=enabled bit6..3 reserved bit2 CCLK - core clock 1=1/2external bus clock, if bus is idle, 0=normal bit1..0 clock mode core/bus ------------------------------------------------------------------------------ CDR 20h chip debug register bit7 LSO - load/store ordering 1=strong, 0=weak bit6 BTBTR - enable BTB test register 1=enabled, 0=disabled bit5 reserved bit4 MLR - enable reordering of misaligned loads 1=enabled, 0=disabled bit3 AIS - enable all instructions stalled to serialize pipe 1=enabled, 0=disabled bit2 LOOP - enable loopmode 1=enabled, 0=disabled bit1 BTB - enable BTB 1=enabled, 0=disabled bit0 RS - enable return stack 1=enabled, 0=disabled ------------------------------------------------------------------------------ ??? 60h unknown register ??? 61h unknwon register ------------------------------------------------------------------------------ SMAR CD..CFh SMM address region (see description above!) ------------------------------------------------------------------------------ DIR0 FEh device identification register #0 (see description above!) DIR1 FFh device identification register #1 (see description above!) A DIR1 value of 13h indicates the revision 1.30, as 15h indicates a revision 1.50 processor. I don't know how the sub-stepping (so i.e. 1.41 or 1.42) can be differed. Do you? ------------------------------------------------------------------------------ === Cut === , --- p /2 2.50.A0715+ * Origin: Boggy Place. Troitsk. (2:5095/9)

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