Topic AMD_TECH from CPU FAQ base

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SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Aleksandr Konosevich 2:5004/9 Sat 14 Oct 95 17:36 Subj : ., ? p p, p , p p , p ... [...] Am486(R) Microprocessor Design. Application Notes. Page 3. Table 2. Microprocessor Pinout Differences Pin # Am486DX4 Future Am486DX2 Am486DX2 169-pin i486DX2 i486DX4 CPU w/b enh. CPU (5V) CPU (3V) OverDrv SL-Ehh. CPU Socket A-10 INC INV INC INC INC INC INC A-12 INC HITM# INC INC INC INC INC A-13 INC INC INC INC FERR# INC INC B-10 INC SMI# INC INC SMI# SMI# SMI# B-12 INC CACHE# INC INC INC INC INC B-13 CLKMUL WB/WT# INC CLKMUL INC INC INC B-14 TMS TMS TMS TMS UP# TMS TMS C-10 INC SRESET INC INC INC SRESET SRESET C-12 INC SMIACT# INC INC SMIACT# SMIACT# SMIACT# C-14 FERR# FERR# FERR# FERR# INC FERR# FERR# G-15 INC STPCLK# INC INC STPCLK# STPCLK# STPCLK# J-1 INC INC Vcc INC Vcc/Vcc5 Vcc Vcc5 R-17 INC CLKMUL INC INC INC/CLKMUL INC CLKMUL S-4 VOLDET VOLDET NC VOLDET NC/VOLDET NC VOLDET NOTES : 1.When using the 237-pin version, refer to the next higher number and later (i.e. A-13 = B-14) 2. The INC indicates a design change from NC pinout specification in the published data sheets. 3. Pin B-13 MUST BE connected to Vss for proper operation of current Am486DX2 microprocessor product. 4. Pin R-17 MUST BE connected to Vss for proper operation of future Am486DX2 microprocessor products. >< IMHO, Cx486DX4-GP4 pinout' i486DX4. , >< p SMM hardware- - a-la Cyrix & a-la SL-Intel, >< p 3 CCR3. [...] Page 5. Table 1. Processor Revision ID Values in DX Register after RESET Processor type Am486 CPU i486 CPU DX2 043x 043x DX4 048x* 048x DX2 w/b enh. 047x 047x DX4 w/b enh. 049x N/A * Initial versions of the Am486DX4 microprocessor have a waiver that indicates that the CPU ID code matches that of the DX2 processor. Figure 1. CPU ID Determination CHECK FOR ID CODE : Read and store DX immediately after RESET | V DETERMINE CPU OPERATING SPEED : Run timing loop and store operating speed value. | V IS ID = 043x AND SPEED = 100 MHz ? ---> YES ---> CPU is Am486DX4-100 processor | with waiver. V NO | V IS BIT 21 OF EFLAGS ---> YES ---> CPU is current Am486 processor READ ONLY ? or early Intel processor. Use | reported Processor Revision ID. V NOTE : This CPU does not support NO the CPUID instruction. | V RUN CPUID INSTRUCTION ------------> CPU is current Intel processor TO OBTAIN VENDOR AND or future AMD processor. See CPU ID INFORMATION appropriate data sheet for detailed information. >< H, p Cyrix' : p DIR0 - p >< , pp. RESET' ... :) With best wishes, Aleksandr --- * Origin: p p ... :E (2:5004/9) SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Sergey Kutikin 2:5020/324.16 Sun 17 Dec 95 06:30 Subj : Am5x86...To be continued...? p ! " CPU ID in DX at Reset Comments Am5x86 CPU at 133 or 160 MHz 04Exh WT Cache 04Fxh WB Cache Am5x86 CPU at 150 MHz 048xh WT Cache 049xh WB Cache " ("AMD BIOS Development Guide" CPU Identification Algorithm p.7) Best regards,Sergey --- GEcho 1.11+ * Origin: Net v zhizni schastya... (2:5020/324.16)

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