Topic AMD_K5 from CPU FAQ base


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SU.HARDW.PC.CPU (2:5020/299) SU.HARDW.PC.CPU From : Aleksandr Konosevich 2:5004/9.7 Thu 19 Jan 95 09:26 Subj : . ... . p ... ;))) "Appendix H" P5 AMD- K5 : ------------------------------------------------------------------------------ From: Tim Hostetter To: Aleksandr K. Konosevich (IPM Return Requested) In-Reply-To: Aleksandr: In response to your questions: 1) There is no complete documentation about K5 yet, however, K5 is pin for pin compatible with Pentium P54C, with the exception of multiprocessor support. Therefore, the Pentium literature does apply as far as programming is concerned. K5 is a 3.3v processor in a 296 pin staggered PGA package. The main architectural differences are that K5 is a four issue machine, compared to P54C two issue. K5 has 16k internal instruction cache and 8k data cache, 4 way set associative supporting the MESI protocol. K5 also has elaborate branch prediction and speculative decode logic. Overall performance improvement over Pentium is estimated to be around 30% at the same clock frequency running the same code. 2) I don't know many details about the P5 microcode patch capability. K5 does have a microcode patching feature, but like P5, the details are confidential, at least for now. 3) K5 does support a two pin SMM feature. It is the same as P54C. Hope this helps. Regards, Tim Hostetter K5 Team Leader, System Silicon Validation ------------------------------------------------------------------------------ p p p, ... p P5 K5 p pp ... ;)))))))) With best wishes, Aleksandr --- * Origin: aleks@sibkom.omsk.su (2:5004/9.7)

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