Topic 486XLC from CPU FAQ base


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SU.HARDW.PC.MOTHERBOARD (2:5020/75.7) SU.HARDW.PC.MOTHERBOARD From : Vitalic Zagorodnuk 2:5020/168.300 Mon 08 Nov 93 11:42 Subj : 486DLC Hello All! MB351 Cyrix486DLC-40 p. 15700 DryStones p 11838 - p 40 MHz. p TI Cx p - p? LEA POPAD p, p? p p p { ; This is a small description of 486DLC from "TI application notes" ; ... ; The configuration registers are accessible through an index data registers ; pair at I/O address 22h and 23h ; index==22 , data==23 CRout macro index,value mov al,index out 22h,al mov al,value out 23h,al endm ; Configuration Control Register 0, index=C0, default=0 ; bit7 Suspend ; bit6 CO (2 way set organization) ; bit5 Barb 1 = on HOLD cache is invalidated to avoid DMA problems ; bit4 Flush ; bit3 KEn ; bit2 A20M 1 = A20 mask ON ; bit1 NC1 1 = A0000-FFFFf is noncacheble ; bit0 NC0 1 = the 1st 64Kb block of each 1Mb is noncacheble ; ; Configuration Control Register 1, index=C1, default=0 ; bit7 Rpl ; bit6 reserved ; bit5 reserved ; bit4 reserved ; bit3 reserved ; bit2 reserved ; bit1 reserved ; bit0 reserved ; ; * SLC Each of noncacheble region registers consist of two 8 bit registers, ; 12 bits are the address bits A23-A12 of the region starting address and ; 4 bits explain the block size. ; ; * DLC Each of noncacheble region registers consist of three 8 bit registers, ; 20 bits are the address bits A31-A12 of the region starting address and ; 4 bits explain the block size. ; ; SLC address region register ARR1 index=C5 ; bits 15-4 A23-A12 ; bits 3-0 BS3-BS0 ; ; SLC = ARR2 is a index C8h..C9h, ARR3 at CBh..CCh, ARR4 at CEh..CFh ; DLC = ARR2 is a index C7h..C9h, ARR3 at CAh..CCh, ARR4 at CDh..CFh ; ... ; model tiny .8086 .code org 100h start: ; This program enable 486DLC cache ifdef Cache .486p cli mov eax,cr0 or eax,40000000h ; turn off cache mov cr0,eax invd ; flush internal cache CRout 0C0h,14h CRout 0C1h,00h CRout 0C4h,00h ; Non-cacheble CRout 0C5h,0Ah ; start=A000 CRout 0C6h,06h ; size=128Kb CRout 0C7h,00h ; Non-cacheble CRout 0C8h,0Ch ; start=C000 CRout 0C9h,07h ; size=256Kb CRout 0CAh,00h CRout 0CBh,00h CRout 0CCh,00h CRout 0CDh,00h CRout 0CEh,00h CRout 0CFh,00h ret endif ; This program demonstrate how to determine 486DLC CPU mov dx,offset MsgMain call Print xor dx,dx ; set flags to known value pushf pop cx ; load flags into CX mov ax,-1 mov bx,4 div bx pushf pop ax mov bx,08D5h ; Mask for flags and ax,bx and cx,bx cmp ax,cx mov dx,offset MsgNotFound jne Print .386p mov eax,cr0 push eax and al,0EFh mov cr0,eax mov eax,cr0 test al,10h @@486DLC: mov dx,offset MsgDLCfound jz @@restore mov eax,cr0 or al,010h mov cr0,eax mov eax,cr0 test al,10h jz @@486DLC mov dx,offset MsgDLCfound @@restore: pop eax mov cr0,eax .8086 Print: mov ah,9 int 21h ret MsgMain db 'I am looking for TI486 or Cyrix486. ','$' MsgNotFound db 'Sorry. Such CPU not found',13,10,'$' MsgDLCfound db '486DLC found!',13,10,'$' MsgSLCfound db '486SLC found!',13,10,'$' end start } italic, ;-F --- Yet another GoldED 2.41+ * Origin: SBS-Net, Moscow, Russia (2:5020/168.300) SU.HARDW.PC.MOTHERBOARD (2:5020/299) SU.HARDW.PC.MOTHERBOARD From : Yuric Hapochkin 2:5020/68.8 Thu 19 May 94 19:09 Subj : 486DLS or 486SX25 . y ??? Hello Nikolaj! Tuesday May 10 1994 01:58, Nikolaj Eroshenkov wrote to Alexander Gorunov: AG>> ! RT_F_M ! H - DOOM - NE> aaee xaep MIPhT, a eo a. He ao e a NE> po ooapaey y. o e coce o-aoc. e caa . TI486DLC & TI486SLC ( TI486 Microprocessor Reference Guide). NE> ooo co oy ee pa oop : BCE ABCT OT COCTOH TA 5 NE> B HEKCE 0 PECTPA 22 !!! A ace DOOMa a. T e a co 30% . ( TI486 Microprocessor Application Note 1993) , Configuration Control Register 0 0C0h ( ), ? , __ . bit 0 - NC0 bit 1 - NC1 bit 2 - A20M bit 4 - FLUSH bit 5 - BARB Software _only_ solutions. bit 5 ( ) - [..] It switches the TI486 CPU in a mode, where all the cache entries are invalidated (the cache is flushed) when the CPU enters the HOLD mode.This solution has little impact on performance because the cache is empty after _each_ DMA-cycle but it avoids any possible DMA conflict _without_modifying_hardware_. ( ) bit 0 - [.] forces the first 64 KB block at each 1 MB boundary to non-cacheable [..] This bit avoids any problem using A20 mask. ( BIOS, - , ) TI486DLC/SLC 386DX/SX , . : ( ) ? .... , bit 2 bit 4 [ ] ( ;-( DMA- , A20GATE#. DLC/SLC i486DX/SX __ . ! :) NE> oo ceye : cpe copoc a ISA (1.5+6)/2 = 3.75 /c, NE> VLB - (12+26)/2 = 19 eo. Bxo, o cpee VLB cpee ISA ... :((( , , , , ISA 6 / , ,

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